This disclosure relates to the execution of instructions in a multi-threaded computing environment, and, more specifically, to the use of instruction buffers in a multi-threaded environment.
A computer processor that supports two or more software threads uses various hardware structures to facilitate execution of instructions. An instruction fetch unit (IFU), for example, may retrieve instructions from cache and/or other memory structures of a computer system, and then pass those instructions down a pipeline to other hardware units for execution.
An IFU may have a pool of buffered instructions so that upon an indication that an instruction should be advanced for execution, the IFU is able to provide that instruction to an execution pipeline without actually having to fetch from cache. The size of this pool of buffered instructions may vary in accordance with the fetch latency of the IFU (i.e., the number of cycles it takes for the IFU to retrieve instructions from cache). A significant amount of chip space may be used by such a pool of buffered instructions.